Double Fault Tolerant Full Adder Design using Fault Localization
Also Available Domains Arithmetic Core|Xilinx Vivado
Abstract
In the era of advanced microelectronics, rate of chip failure is increased with increased in chip density. A system must be fault tolerant to decrease the failure rate. The presence of multiple faults can destroy the functionality of a full adder and there is a trade-off between number of fault tolerated and area overhead. This paper presents an area efficient fault tolerant full adder design that can repair single and double fault without interrupting the normal operation of a system. In this approach, self-checking full adder is used detecting the fault based on internal functionality. This makes the method efficient in term of area and number of fault tolerated when compared to the existing designs.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Hardware requirement
Processor - Pentium –III
Speed - 1.1 GHz
RAM - 1 GB (min)
Hard Disk - 40 GB
Floppy Drive - 1.44 MB
Key Board - Standard Windows Keyboard
Mouse- Two or Three Button Mouse
Monitor - SVGA
Software requirements
v Operating System :Windows95/98/2000/XP/Windows7
v Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
v This software’s where Verilog source code can be used for design implementation.
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- About approximation computing
- About Reversible logic
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation
· Generation of Netlist.
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
