Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, it is necessary to protect memory cells using protection codes. Various error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper Decimal Matrix Code (DMC) is proposed to detect and correct multiple bit errors. The proposed DMC utilizes 64-bit decimal algorithm to increase the error correction capability compared to 32- bit decimal matrix code. Moreover, the encoder reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed scheme has a superior protection level against large MCUs in memory