DESIGNING OF ARRAY MULTIPLIER BY USING MEMORY ELEMENT AND MEMRISTOR FOR LOW POWER CONSUMPTION

Array multipliers are widely used in digital signal processing, image processing, and arithmetic operations due to their regular structure and ease of implementation. However, conventional CMOS-based array multipliers suffer from high power consumption and increased area as technology scales down. To address this challenge, this project proposes the design of a low-power array multiplier by incorporating memory elements and memristors into the architecture. The memristor-based design reduces transistor count, minimizes leakage power, and provides non-volatile storage capability, while memory elements improve computational efficiency by reducing redundant switching activity. The proposed design is analyzed in terms of delay, power consumption, and area using simulation tools. Comparative results with traditional CMOS array multipliers show significant improvements in power efficiency with minimal impact on performance, making the design suitable for energy-efficient VLSI and in-memory computing applications.