Design & Verification of AMBA AHB-Lite Memory Controller
Objective
The main aim of this project is to implement AMBA-3AHB lite to perform read/write operations
Abstract
As technology advances, the on-chip communication bus architecture becomes increasingly prominent in interconnecting various components within the System-on-Chip (SoC). The standard ARM AMBA on-chip interconnect bus is designed as an SoC system’s high-performance backbone bus, which supports faster communication with internal and external memories. This paper presented a memory controller design with an AMBA 3 AHB Lite standard based on a single master and multiple slave model.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx ISE14.7 Suite/Vivado2018.3 Tool.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
· 100 MB of available disk space.
Learning Outcomes
• Basics of Digital Electronics
• FPGA design Flow
• Introduction to Verilog Coding
• Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
• Drawbacks of existing methods
• Applications in real time
• Xilinx ISE 14.7/Xilinx Vivado for design and simulation
• Generation of Netlist
• Solution providing for real time problems
• Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills
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