Design of Two Interleaved Error Detection and Corrections using Hsiao Code and CRC

Project Code :TVMAFE552

Objective

In this paper, we present two interleaved Double-Adjacent-Error Corrections (DAECs) for Error Detection and Correction (EDAC), using the Hsiao Code and Cyclic Redundancy Code (CRC).

Abstract

A radiation-induced single-event upset (SEU) is a major disruption to electronics operating in satellites. If not rectified, a single-bit-error can become uncorrectable. In this paper, we present two interleaved Double-Adjacent-ErrorCorrections (DAECs) for Error Detection and Correction (EDAC), using the Hsiao Code and Cyclic Redundancy Code (CRC). From our results, both EDACs can correct 100% of the single-bit-errors, double-adjacent-bit-errors, and detect doublebit-errors and up to four-adjacent-bit-errors. The Hsiao Code EDAC encoder design requires less bit-weight than the CRC EDAC, which is an attribute of a high-speed EDAC. The CRC EDAC, in contrast, has a higher error detection rate for both three- and four-bit-errors. We also propose two storage formats and algorithm designs that can manage and store the 48-bit codeword in 8-bit and 16-bit memory devices, a typical satellite scenario where board space is scarce.

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Block Diagram

Specifications

Software Requirements:

Xilinx Vivado Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to error correction design
About CRC
Knowledge on Hsaio code
Knowledge on error detection
About interleaving concept
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice