Design of Three Stage Dynamic Comparator with Tail Transistor using 20nm FinFET Technology for ADCs

Name: Takeoff Edu Group
Address: 6-2-85/B, Old Maternity Hospital Rd, Thyagaraja Nagar, Nehru Nagar, Tirupati, 517501, IN
Telephone: 9030333433

Also Available Domains Cadence EDA

Project Code :TVPGTO838

Objective

The proposed design of Modified three stage comparator by using the tail transistor has been implemented to achieve the lower leakage power consumption and reducing the short channel effects.