Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates

The primary aim is to reduce power consumption and minimize test time. Power consumption presents a significant challenge for portable devices, which require extended operation and minimal charging intervals. This issue is particularly critical in handheld communication systems and battery-operated devices, such as laptops, mobile phones, pacemakers, multimedia products, and cellular phones. Reducing power consumption has become a crucial focus in the electronics industry, especially for test power reduction, and remains a popular area of research. One approach explored is the use of scan chain architectures, which are essentially sequences of flip-flops designed to simplify circuit testing and monitoring. By shifting test data in and out, scan chains enable efficient comparison of outputs. These architectures typically use flip-flops modified for testability by incorporating a multiplexer before the input terminal, allowing for selection between the standard input and the test input. The circuit has been optimized to reduce average power consumption and was designed and analyzed using the Cadence Tool under various operating conditions to assess factors impacting test time and power usage.

Keywords: — Design for testability (DFT), Built in self-test (BIST), Scan chain, Low power logic, CMOS Transmission gates