DESIGN OF SPI AND I2C PROTOCOL IN VERILOG HDL

The SPI bus is a synchronous serial interface data bus with full duplex, few signal lines, simple protocol, and fast transmission speed. Based on these characteristics, parallel high-speed computing with FPGA is used to meet device expansion and experiment in high-rate environments. This paper introduces the structure and working principle of SPI communication bus, analyzes its timing structure and four working modes, and uses this state machine method to realize its SPI bus communication function & also this paper focuses on the design of I2C single master which consists of a bidirectional data line i.e. serial data line (sda) and serial clock line (scl). This protocol has the ability to support multiple masters. I2C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices and is used for faster devices to communicate with slower devices and each other without data loss. It requires only two lines for communication with two or more chips and can control a network of device chips with just two general purpose I/O pins whereas, other bus protocols require more pins and signals to connect devices. The module circuit of SPI & I2C is written by Verilog hardware description language, and the waveform is simulated in vivado simulator. After the simulation waveform analysis, the feasibility of the state machine method is verified.