Design of RISC & MIPS Architecture
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
The design of high-performance processors with very low power requirements is the primary goal of many contemporary and futuristic applications.
Abstract
Systems demand a high-performance low-power processor that can execute the instruction without draining much power form the battery. In the last four decades, processor performance has increased through CMOS scaling. But now it is coming to its end as CMOS technology is approaching physical limitations. The design of high-performance processors with very low power requirements is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture that is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA) size.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements
· Modelsim
· Xilinix ISE 14.7
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to processor design
- Knowledge on RISC and MIPS
- About approximation computation
- About error reduction
- About constant truncation
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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