Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions
Also Available Domains Xilinx Vivado|Xilinx ISE|Cadence EDA
Objective
The main aim of this project is to reduce the power in sequential circuit by using reversible logic gates. The new reversible gates are realized by fredkin, feynman, toffoli gates
Abstract
In this project, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed–Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Xilinx ISE 14.7
- HDL: Verilog
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- FPGA design Flow
- Introduction to Verilog Coding.
- Different modeling styles in Verilog
- Data Flow modeling
- Structural modeling
- Behavioral modeling
- Mixed level modeling
- Combinational & Sequential circuits
- Knowledge on Approximate computing
- Arithmetic Circuits
- Applications in real time
- Xilinx ISE 14.7 for design and simulation
- Generation of Netlist
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
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