Design of Reversible MAC Unit, Shift and Add Multiplier using PSDRM Technique

Project Code :TVPGFE153

Objective

The design of an Error Tolerant (ET) Shift-and Add Multiplier is done. It utilizes the concept of error tolerant addition for accumulation of partial products and a ring counter for shifting of multiplier bits and partial product.

Abstract

Reversible logic has become very promising for low power design using emerging computing
technologies. Sequential circuits can be built by replacing the latches, flip-flops and associated
combinational gates of the traditional irreversible designs by their reversible counter parts. Since it leads to high quantum cost and garbage outputs this replacement technique is not very promising. It is possible to design synchronous sequential circuits directly from reversible gates using pseudo Reed– Muller expressions representing the state transition and the output functions of the circuit. The multiplication and accumulation (MAC) are the important operations involved in almost all the Digital Signal Processing applications. Accumulator in this MAC unit will be
designed using PSDRM technique. And Multiplier is the fundamental components of many digital and non digital systems and hence, their power dissipation is the prime concern. The design of an Error Tolerant (ET) Shift-and Add Multiplier is done. It utilizes the concept
of error tolerant addition for accumulation of partial products and a ring counter for shifting of multiplier bits and partial product. Shift register used to shift multiplier bits and partial product is designed using Pseudo Reed Muller expression.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Hardware requirement

Processor - Pentium –III

Speed - 1.1 GHz

RAM - 1 GB (min)

Hard Disk - 40 GB

Floppy Drive - 1.44 MB

Key Board - Standard Windows Keyboard

Mouse - Two or Three Button Mouse

Monitor - SVGA

Software requirements

v Operating System :Windows95/98/2000/XP/Windows7

v Front End : Modalism 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation

v This software’s where Verilog source code can be used for design implementation.

Learning Outcomes

Understanding Reversible Logic: Gain a thorough understanding of reversible logic gates and circuits, including the principles and advantages of reversible computation.
Reversible MAC Unit Design: Acquire knowledge and skills related to the design of a reversible MAC unit, which performs the multiplication and accumulation of operands in a reversible manner.
Shift and Add Multiplier Design: Learn the principles and techniques for designing a shift and add multiplier, which is a common method for implementing multiplication operations.
Familiarity with PSDRM Technique: Become familiar with the PSDRM technique, which is a specific approach to designing reversible logic circuits using the concepts of self-duality and Reed-Muller expansions.
Implementation of Reversible Circuits: Gain hands-on experience in implementing the designed reversible MAC unit and shift and add multiplier using the PSDRM technique, using a hardware description language (HDL) or a logic synthesis tool.
Reversible Circuit Optimization: Explore various optimization techniques for reversible logic circuits, such as gate count reduction, quantum cost minimization, and power optimization, to improve the performance and efficiency of the designed circuits.
Analysis and Evaluation: Learn how to analyze and evaluate the performance metrics of the designed circuits, such as gate count, circuit delay, power consumption, and area utilization, and assess their suitability for specific applications.
Problem-Solving Skills: Enhance problem-solving skills by addressing challenges and complexities associated with the design of reversible MAC units and shift and add multipliers, including trade-offs between circuit complexity, performance, and efficiency.
Research and Literature Review: Develop the ability to conduct research and review relevant literature on reversible logic, MAC units, shift and add multipliers, and the PSDRM technique, to stay updated with the latest advancements in the field.
Communication and Documentation: Practice effective communication and documentation skills by presenting the design methodology, results, and findings of the reversible MAC unit and shift and add multiplier using the PSDRM technique in a clear and concise manner, both orally and in written reports or papers.