Design of Power-Efficient Posit Multiplier

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE90

Objective

The major contribution of this work is to implement a power-efficient posit multiplier architecture which divides the mantissa multiplier into small portions. Thus the proposed method is suitable to be used in any low power posit arithmetic unit designs

Abstract

Posits are a tapered precision number system to replace IEEE floating point. It provides more precision, lower complexity, and lower power implementations than IEEE floating point. In this project, a power efficient posit multiplier architecture is proposed. The mantissa multiplier is still designed for the maximum possible bit-width; however, the whole multiplier is divided into multiple smaller multipliers. Only the required small multipliers are enabled at run-time. Those smaller multipliers are controlled by the regime bit-width which can be used to determine the mantissa bit-width. By using this method, power reduction can be achieved with negligible area.

Keywords: Posit number system, posit multiplier, computer arithmetic, low-power arithmetic circuit

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7/Xilinx Vivado
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding.
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Posit Multiplier
Knowledge on floating point arithmetic
Basics of Leading one detector circuit
Knowledge on Leading zero detector
Knowledge on Comparators
Knowledge on carry propagation adder
Concept of Rounding technique
How to achieve high speed, Low power and Area efficiency?
Scope of approximation concept in today’s world
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing