Design of Power and Area Efficient Approximate Multipliers

Posits are a tapered precision number system to replace IEEE floating point. It provides more precision, lower complexity, and lower power implementations than IEEE floating point. In this project, a power efficient posit multiplier architecture is proposed. The mantissa multiplier is still designed for the maximum possible bit-width; however, the whole multiplier is divided into multiple smaller multipliers. 

Only the required small multipliers are enabled at run-time. Those smaller multipliers are controlled by the regime bit-width which can be used to determine the mantissa bit-width. By using this method, power reduction can be achieved with negligible area. The simulation and synthesis results are carried out using Xilinx ISE 14.7.

Keywords: Posit number system, posit multiplier, computer arithmetic, low-power arithmetic circuit