Design of PLL using improved performance ring VCO

Project Code :TVMABE220

Objective

The proposed ring VCO is based on a modified topology that incorporates a tail current source and a cross-coupled pair of transistors to improve the linearity and phase noise performance.

Abstract

The phase-locked loop (PLL) is a key component in modern communication systems that is used for synchronization, frequency synthesis, and clock recovery. The performance of the PLL depends on the characteristics of its constituent blocks, including the voltage-controlled oscillator (VCO). In this paper, we propose the design of a PLL using an improved performance ring VCO.

The proposed ring VCO is based on a modified topology that incorporates a tail current source and a cross-coupled pair of transistors to improve the linearity and phase noise performance. The design is implemented using a 180nm CMOS process, and simulations are carried out using Tanner EDA.

Key words:-PFD, Dead Zone, VCO, Power, PLL

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tanner EDA
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

· Introduction to Analog Electronics

· Knowledge on VCO

· Basics of PLL

· Learning of Low pass Filter

· Importance of Transistors

· MOS Fundamentals

· NMOS/PMOS/CMOS Technologies

· How to design circuits using Transistor logic?

· Transistor level design for PLL

· How to design low power, high speed area efficient transistor level circuits?

· Scope of PLL in today’s world

· Applications in real time

· Tanner EDA tool for design and simulation

· Solution providing for real time problems

· Project Development Skills:

· Problem Analysis Skills

· Problem Solving Skills

· Logical Skills

· Designing Skills

· Testing Skills

· Debugging Skills

· Presentation skills

· Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice