This research aims to develop a novel half-adder circuit design for a multiplier, focusing on low power dissipation and area reduction. The innovation lies in implementing Pass Transistor Logic (PTL) to enhance adder logic performance. Compared to previous studies, our design significantly reduces transistors in terms of area, delay, and power consumption. The proposed work decreases the power dissipation of the array multiplier. Simulation results show that the suggested design dissipates power and delay for 10 transistors in half adder logic and dissipates power and delay for 18 transistors in full adder logic. The proposed logic was designed and simulated in a 90 nm CMOS process.

Key words: Full adder, half adder, XOR, AND, Wallace tree multiplier