Design of Low Power and High-Speed MAC Unit for Digital Signal Processing Applications
Objective
The Multiply-Accumulate (MAC) unit is a fundamental computational block in Digital Signal Processing architectures, critical for filtering, convolution, FFT, and neural network inference. Performance of the MAC unit in terms of speed and power directly determines the efficiency of the overall DSP system. This paper presents a low-power, high-speed MAC unit targeting DSP applications using a Vedic mathematics-based Urdhva-Tiryakbhyam multiplier integrated with a flag-driven Selective Partial Sum (SPS) adder that suppresses redundant carry propagation and minimizes switching activity
Abstract
The Multiply-Accumulate (MAC) unit is a fundamental computational block in Digital Signal Processing architectures, critical for filtering, convolution, FFT, and neural network inference. Performance of the MAC unit in terms of speed and power directly determines the efficiency of the overall DSP system. This paper presents a low-power, high-speed MAC unit targeting DSP applications using a Vedic mathematics-based Urdhva-Tiryakbhyam multiplier integrated with a flag-driven Selective Partial Sum (SPS) adder that suppresses redundant carry propagation and minimizes switching activity. Implemented in Verilog HDL and synthesized on a FPGA using Xilinx vivado , significantly outperforming conventional MAC architectures.
Keywords: MAC Unit, Multiply-Accumulate, Low Power, High Speed, DSP, Vedic Multiplier, FPGA, Urdhva-Tiryakbhyam
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Block Diagram
Specifications
Software Requirements
• Xilinx Vivado
• Verilog HDL / VHDL
Hardware Requirements
• Xilinx FPGA (Basys-3 / Nexys A7)
• Oscilloscope
• Logic Analyzer
Learning Outcomes
• MAC Architecture Design and Optimization
• Vedic Multiplier Implementation
• Low Power Adder Design Techniques
• FPGA-Based DSP System Development
• High-Speed Arithmetic for Signal Processing
Paper Publishing
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