Reversible logic is a prominent technology in Quantum computing technology. The devices used by this technology operate at ultra high speed and consume very low power.
In this project different reversible logic gates have been discussed and designed. Reversible logic is a predominant structure in Quantum computing technology. The device which uses this technology have many advantages such as they operate at ultra-high speed and also consume very less power. In the proposed work we have designed basic reversible logic gates which are implemented using hardware description language or Verilog HDL to be precise. The Wallace tree multiplier is implemented using basic half adder and full adder using verilog. GCD processor is also implemented using verilog. The reversible logic gates are designed and a 4bit reversible adder, irreversible adder along multiplier is designed. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications:
Software Requirements:
· Xilinx vivado2018.3 Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes:
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation
· Generation of Netlist.
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills