Design of Low-Area and High Speed Pipelined Single Precision Floating Point Multiplier

Project Code :TVPGFE328

Objective

This paper explains a 32-bit binary Floating Point Multiplier (FPM) architecture using an area efficient array multiplier.

Abstract

Floating point multiplication is a common operation in advance Digital Signal Processing (DSP) applications. This paper explains a 32-bit binary Floating Point Multiplier (FPM) architecture using an area efficient array multiplier. The proposed multiplier generates only the needed MSB bits of the product mantissa by making use of Divide and Conquer (D&C) algorithm with a modified Full Adder (FA) to increase the speed of multiplication. The pipeline architecture is also proposed to improve the performance of the multiplication in terms of reduced delay and power. The proposed FPM is compared with booth recoding based FPM and the various performance measures such as area, power and delay are analyzed.

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Block Diagram

Specifications

Software Requirements:

· Xilinx ISE14.7 Suite/Vivado2018.3 Tool.

· HDL: Verilog.

Hardware Requirements:

· Microsoft® Windows XP.

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.

· 512 MB RAM.

· 100 MB of available disk space.

Learning Outcomes

Basics of Digital Electronics.
Concept of floating point representation.
Difference between floating and fixed point representation.
Introduction to Verilog Coding.
Different modeling styles in Verilog.

o Data Flow modeling.

o Structural modeling.

o Behavioral modeling.

o Mixed level modeling.

Introduction to single precision floating point arithmetic unit design.
About arithmetic operations on floating point numbers.
Knowledge on single and double floating point precision unit’s representation.
Knowledge on non-restoring division algorithm.
About approximation computing.
Applications in real time.

· Xilinx ISE 14.7 Suite/Vivado2018.3 for design and simulation.

· Generation of Netlist.

· Solution providing for real time problems.

· Project Development Skills:

o Problem Analysis Skills.

o Problem Solving Skills.

o Logical Skills.

o Designing Skills.

o Testing Skills.

o Debugging Skills.

o Presentation Skills.

o Thesis Writing Skills.

Demo Video

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Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing