Also Available Domains Arithmetic Core|Xilinx ISE
The main objective of this project is to design the multiplier by using higher order compressors in partial product reduction stage. By using approximate compressors, the area and power will be reduced
Approximate or inexact computing is a computing paradigm that can trade energy and computing time with accuracy of output. Imprecise multiplier has been widely studied for image processing applications, imprecise multiplication is done through compressors. While performing the multiplication with large word length, we will consider higher order compressors which will reduce the reduction stages in multiplication. In this paper 8:2 compressor is deigned and a novel comparison technique is developed for approximation. This novel 8:2 compressor is used in 16 bit multiplier and compared with the existing multiplier. The novel compressor will give the better performance in terms of area, delay and power. The proposed multiplier is used in image multiplication applications.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
· Xilinx Vivado Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space