Design of High Performance and Low Power Multiplier using Modified Booth Encoder

In this paper, we proposed a high speed low-power multiplier adopting the new SPST technique. This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high performance and low-power purposes. Here the multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted additions and thus minimizes the switching/dynamic power dissipation. Low-power multipliers are very important for reducing energy consumption of digital processing systems. The main purpose of a good multiplier is to provide a physically compact, high speed and low power consuming chip. The proposed high speed low power multiplier can attain better improvement in speed and power reduction in the modified booth encoder when compared with the conventional array multipliers.