Design of High Performance and Low Power Multiplier using Modified Booth Encoder

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE287

Objective

The main aim of this project is to implement a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by using the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate.

Abstract

In this paper, we proposed a high speed low-power multiplier adopting the new SPST technique. This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high performance and low-power purposes. Here the multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted additions and thus minimizes the switching/dynamic power dissipation. Low-power multipliers are very important for reducing energy consumption of digital processing systems. The main purpose of a good multiplier is to provide a physically compact, high speed and low power consuming chip. The proposed high speed low power multiplier can attain better improvement in speed and power reduction in the modified booth encoder when compared with the conventional array multipliers.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE/Xilinx Vivado tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Arithmetic circuits
About radix-4 booth encoding logic
Knowledge on adder circuits
SPST adder/subtractor
Knowledge on partial product generation and reduction
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing