Design of Half Adder Domino Circuit Using Sleep and Twist-Connected Transistors With Dual Keeper

Abstract

This work presents the design of a Half Adder domino circuit incorporating sleep transistors and twist-connected transistors with a dual keeper technique to achieve low power consumption, high noise immunity, and reliable performance. Conventional domino logic circuits often suffer from excessive leakage current, charge sharing, and reduced robustness under deep submicron technologies. To address these challenges, the proposed design introduces sleep transistors to minimize static power dissipation, while twist-connected transistors improve switching activity and noise tolerance. Additionally, the dual keeper mechanism ensures strong logic level retention and eliminates the problem of charge leakage in dynamic nodes. The Half Adder circuit is implemented using advanced CMOS technology and analyzed for key performance parameters such as propagation delay, power dissipation, power-delay product (PDP), and noise immunity. Simulation results demonstrate that the proposed Half Adder design significantly outperforms conventional domino logic implementations in terms of speed and energy efficiency. This approach is highly suitable for low-power arithmetic units and VLSI applications operating in nanoscale technologies.