Design of Half Adder Domino Circuit Using Sleep and Twist-Connected Transistors With Dual Keeper

Also Available Domains Cadence EDA

Project Code :TVPGTO840

Objective

In this paper, two circuits, namely Half Adder with twist-connected transistors based NOT (T-NOT) gate and Sleep Transistor (HTS) and Half Adder with T-NOT, Sleep Transistor, and Dual Keeper (HTSD) are presented, in order to achieve low power consumption and high speed.

Block Diagram

Specifications

Software Requirements:
• Tool: Cadence

Hardware Requirements:
• Microsoft® Windows XP
• Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
• 512 MB RAM
• 100 MB of available disk space

Learning Outcomes

Learning Outcomes of “Design of Half Adder Domino Circuit Using Sleep and Twist-Connected Transistors With Dual Keeper”

Understanding the working principles of domino logic and its challenges in deep submicron CMOS technology.
Ability to design and implement Half Adder circuits using advanced low-power techniques.
Knowledge of sleep transistor integration for reducing static leakage power in dynamic logic circuits.
Familiarity with twist-connected transistors and their role in improving switching activity and noise tolerance.
Practical skills in applying dual keeper techniques for enhanced charge retention and noise immunity.
Experience in evaluating circuit performance metrics such as propagation delay, power dissipation, and power-delay product (PDP).
Ability to analyze trade-offs between speed, power, and robustness in domino logic circuits.
Competence in using simulation tools (e.g., Cadence, Tanner, LTSpice) for transistor-level design and verification.
Preparedness to design energy-efficient arithmetic building blocks for low-power VLSI systems.
Enhanced problem-solving and critical thinking skills for tackling leakage and reliability issues in nanoscale digital design.