In this project, a full adder and a parity generator circuit is presented using the proposed reversible logic gate in QCA technology. As stated in the Moore’s law the transistor level should get double in every two years, researches is being carried out to find different technology to replace VLSI. QCA technology is the standout among and giving a better solution because it is a nano-technology. It provides high speed, low power consumption and higher density as compared to CMOS technology. The reversible logic gates in QCA are useful in reducing energy dissipation. Here in the proposed work a novel design for reversible logic gate is proposed which can be used as a full adder, even or odd parity generator as well. The proposed circuit is simple in structure to construct and it doesn’t produce any garbage value too. We have used very less number of clock cycles or zones while making this circuit and also it is suitable for implementing other logical gates. The whole project is implemented and verified by simulating it in QCA Designer & QCA DesignerE tools.

Keywords: full adder, parity generator, reversible logic gate, QCA technology, Moore’s law, VLSI, nano technology, energy dissipation, QCA Designer, QCA DesignerE.