Design of Area Efficient and Low Power 4-bit Multiplier Based on Full- Swing GDI Technique
Also Available Domains Transistor Logic|Tanner EDA
Objective
This paper presents a design of 4-bit multiplier using full adder cell based on full swing gate diffusion input technique.
Abstract
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Block Diagram
Specifications
Software Requirements:
Ø Cadence Virtuoso
Ø Technology used: 45nm GPDK
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Introduction to GDI
- Need of MOD GDI in Core memory applications
- Transistors & its applications
o Types of Transistors
o Logic Gates using Transistors
o Pull Up and Pull Down networks
o Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for Full Adders using GDI
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Scope of Mod GDI in today’s world
- Applications in real time
- Cadence tool for design and simulation
- Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation skills
o Thesis Writing Skills
Paper Publishing
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