Design of Area Efficient and Low Power 4-bit Multiplier Based on Full Swing GDI Technique

This paper presents a design of 4-bit multiplier using full adder cell based on full swing gate diffusion input technique. The proposed adder design consists of 18 transistors and compared with different logic styles for full adders through cadence virtuoso simulation based on TSMC 65nm models at a supply voltage of 1v and frequency 250MHz. The simulation results showed that the proposed full adder design dissipates low power while improving the area and provides full swing output voltage among all the designs taken for comparison. The proposed full adder used to design Array, Barun and Baugh Wooley multipliers, Energy and Transistor count of these multipliers improved compared to CMOS.