DESIGN OF APPROXIMATE VLSI ARCHITECTURE FOR ERROR TOLERANT IMAGE PROCESSING APPLICATIONS
Objective
The proposed carry prediction technique can reduce a prediction error rate compared to existing approximate adders considered in this paper.
Abstract
This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. The proposed carry prediction technique can reduce a prediction error rate compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). An excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.
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Block Diagram
Specifications
Software & Hardware Requirements
· Modelsim
· MATLAB
· HDL: Verilog
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to adder design
- Knowledge on adders, gates
- About approximation computation
- About error reduction
- About approximate adders
- About constant truncation
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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