Also Available Domains Xilinx Vivado
This an approximate multiplier with Radix-256 booth based encoding has been suggested. In order to evaluate the booth encoding based on radix-256 a 16 bit approximate multiplier was designed and implemented.
High radix Booth encodings provide significant decrease on the number of partial products in the multiplication. However, due to the generation on hard multiples, additional delay and power are incurred, which in turn hampers the use of high radix Booth encodings. In this brief, an approximate radix-256 Booth encoding is proposed to circumvent the generation on hard multiples. A partial encoding approach is used to produce partial product pairs, which can be obtained easily by simple shifting and complementing operations. The exact encoding values are thus replaced by the sum of each corresponding partial product pair. A 16 × 16-bit multiplier with proposed approximate radix-256 Booth encoding has been implemented for performance evaluation.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications:
Software Requirements:
· Xilinx ISE 14.7 Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes:
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7 for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills