Also Available Domains Arithmetic Core|Xilinx Vivado
In this project, a multiplierless discrete cosine transforms (DCT) design with approximate canonical signed digit (CSD) encoding for image processing is proposed. Two approximation strategies on CSD encoding are proposed in constant multiplication. Based on these two coding approaches, an approximate DCT architecture is presented by taking advantage of the correlation between adjacent pixels of image data. Higher frequency coefficients are gradually ignored from the calculation due to the energy compaction property. Four approximate DCT architectures are thus proposed representing different accuracy levels. The proposed DCTs are implemented using 0.18μm standard CMOS process. The simulation results indicate that the proposed ADCT reduces power and area with a PSNR penalty of 1.6dB when compared with the traditional design. For lossy applications which allow lower computational accuracy, ADCT-III achieves reduction on the power consumption and area, at a cost of 11.7 dB accuracy loss. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE 14.7.
Keywords:- Approximate DCT, CSD encoding, multiplierless, pixel correlation, image processing
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