Design of Approximate Booth Squarer for Error-Tolerant Computing

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE112

Objective

The main objective of this work is to reduce the hardware complexity of partial product generation. Therefore, this article proposes three approximate squarer circuits with an approximation of partial product generation and accumulation for reducing the power consumption

Abstract

The main objective of this project is to explore the benefits of approximate computing, we present an approximate partial product generator squarer (APPGS). By using APPGS, three designs of approximate Radix-4 booth squarer’s (ABS1, ABS2, ABS3) are designed.

The number of least significant columns of approximate partial products are generated by APPGS. ABS2 and ABS3 uses approximate adders and compressors to accumulate the partial products. ABS3 is acts as error recovery module at k number of most significant columns of the approximate partial products. The proposed squarer values of r and k are different.

The proposed squarer ABS1 shows less error rate compared to ABS2 & ABS3. The third design uses an error recovery module to improve the accuracy of the squarer output. The analysis proved that the proposed designs have optimized results for both the hardware and accuracy parameters. The effectiveness of the proposed method is designed using Xilinx ISE 14.7/Xilinx Vivado software.

Keywords: Approximate Booth squarer, approximate computing, approximate partial product generator for squarer (APPGS).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Learning Outcomes

Design of Approximate Booth Squarer for Error-Tolerant Computing
Learning outcomes:
Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Approximate computing
About Booth squarer method
Knowledge on Error metrics
About different adders and compressors
How Booth squarer method is used in Modulation?
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice