Design of Approximate Adder With Reconfigurable Accuracy

Project Code :TVMAFE653

Objective

To design and implement an approximate adder architecture that allows dynamic or reconfigurable control over its accuracy to achieve an optimal trade-off between power consumption, area, delay, and computational accuracy, especially for error-resilient applications such as image processing, machine learning, and IoT devices.

Abstract

Abstract:

In the comparison of 4 x 4 multiplier according to time, area, and speed, Look-Up Tables (LUTs) are used to meet high speed and low power requirements, which are essential in VLSI. In the implementation of Wallace tree, Booth, array multipliers, to identify the most efficient one considering all VLSI aspects. Wallace tree multipliers and Booth multipliers are more effective than array multipliers in terms of delay and power consumption, which makes them more appropriate in area while sacrificing in speed.. But the Wallace tree multiplier is more suitable for FIR filters than other filters. The Xilinx Vivado tool is used to implement Verilog code for generating schematic views of the multipliers, highlighting time, speed, and area characteristics.The FIR filter is implemented using MATLAB software.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx Vivado Tool

· HDL: Verilog

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

o Data Flow modeling

o Structural modeling

o Behavioral modeling

o Mixed level modeling

Introduction to multiplier design
About wallace multiplication
Knowledge on partial product generation and reduction
Knowledge on adders, compressors
About approximation computing
Applications in real time

· Xilinx Vivado for design and simulation

· Generation of Netlist

· Solution providing for real time problems

· Project Development Skills:

o Problem Analysis Skills

o Problem Solving Skills

o Logical Skills

o Designing Skills

o Testing Skills

o Debugging Skills

o Presentation Skills

o Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice