Design of Advanced Encryption Standard using Verilog HDL

Cryptography deals with the security and integrity of the data. Initially many algorithms were developed to encode and decode the data but for securing large and confidential data, the existing algorithms are not reliable, so AES was developed as a new standard for encrypting and decrypting data. Initially it is mainly used to protect highly confidential data, later many applications in networking began using AES as a standard to protect their data. It is primarily used to protect sensitive data, though it is also applied to network backends to enhance data security. AES employs blocks that are 16 bytes long, and its keys can range in size from 128 bits to 256 bits. The main purpose of using Verilog instead of standard VHDL is that it provides very less operation time and the propagation delay to encode and decode the data are comparatively less than other HDL languages. Before AES, DES was used as the encryption standard. The main drawback of DES is that the fixed key size of 56 bits. This problem is solved by AES by providing the flexibility of using required variable key size. Keywords—Advanced Encryption Standard, Input text, Cipher text, Verilog.