Design of A Ring Oscillator Based PUF with Enhanced Challenge Response pair and Improved Reliability

Also Available Domains Communications|Xilinx Vivado|Xilinx ISE|Cadence EDA

Project Code :TVMAFE452

Abstract

Hardware security is of utmost importance nowadays, with the increased number of threats like modelling attacks, reverse engineering and extracting secret information from the IC’s. A physical unclonable function (PUF) is a promising solution to many securities related problems and can be used to produce devices or IC’s that are unique and resistant to cloning attempts. A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects. Various kinds of PUF designs are possible like ring oscillator, SRAM and arbiter PUF’s etc. A Ring oscillator based PUF is designed based on the delays present in the wires that leads to different frequency of oscillation and can form the basis for key generation. They are also easily implemented in field programmable gate array (FPGA).In this paper we propose a ring oscillator based design with enhanced challenge response pair (CRP) with improved reliability .Our design has more number of challenge response pair since all the possible frequency comparisons of the Ro are done .Also it provides better reliability because our approach relies on relative values and not absolute value, it incorporates the difference between the highest frequency in the present comparison and the maximum of all the measured frequencies, under varying environmental conditions even if the absolute value changes, the relative value will never change.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

·         Xilinx ISE 14.7

·         HDL: Verilog

Hardware Requirements:

·         Microsoft® Windows XP,

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space

Learning Outcomes

  • Basics of Digital Electronics
  • FPGA design Flow
  • Introduction to Verilog Coding
  • Different modeling styles in Verilog

o   Data Flow modeling

o   Structural modeling

o   Behavioral modeling

o   Mixed level modeling

  • Concept of oscillators
  • Importance of security
  • Drawbacks of existing methodologies
  •  Introduction to PUF
  •  Knowledge on PUF
  •  Knowledge on various types of PUF
  • Applications of PUFin real time
  • Scope of RO_PUF concept in today’s world
  • Applications in real time

·         Xilinx ISE 14.7/Xilinx Vivado for design and simulation

·         Generation of Netlist

·         Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation Skills

o   Thesis Writing Skills

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