Design of a Parallel Self-Timed Adder by Using Transmission Gate Logic Style

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE235

Abstract

In this paper, the design of a parallel self-timed adder by using transmission gate logic style was implemented for multi bit binary addition. Parallel Asynchronous Self Timed Adder (PASTA) is designed by using transmission gate based on recursive formulation. Multiplexer is used in this design for avoiding difficulties of interconnections. The operation is parallel to avoid carry chain propagation. In carry-look ahead adder due to carry chain propagation there is a problem of high fan-in and fan-out. In this PASTA completion detection unit is present for connecting all carries to avoid high fan-out. A high fan-in is unavoidable for asynchronous logic through transistors is connected in parallel. The simulation results of proposed model attain better power consumption and reduction in number of transistors and results are verified with proposed technique in 180nm, 90nm and 45nm by TANNER EDA tool

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Block Diagram

Specifications

System Configuration:-

In the hardware part a normal computer where Tanner EDA software can be easily operated is required, i.e., with a minimum system configuration

Hardware requirement

Processor - Pentium –III

Speed - 1.1 GHz

RAM - 1 GB (min)

Hard Disk - 40 GB

Floppy Drive - 1.44 MB

Key Board - Standard Windows Keyboard

Mouse - Two or Three Button Mouse

Monitor - SVGA

Software requirements

v Operating System :Windows95/98/2000/XP/Windows7

Tools : Tanner E

Learning Outcomes

Understanding Self-Timed (Asynchronous) Circuit Design: Learners will gain a comprehensive understanding of self-timed circuit design principles, which allow circuits to operate without a central clock, relying on handshaking protocols for data transfer and synchronization.
Transmission Gate Logic (TGL) Architecture: Learners will become familiar with the concept of Transmission Gate Logic and its advantages and limitations compared to other logic styles (e.g., CMOS, TTL).
Asynchronous Adder Design: The paper discusses the design of a parallel self-timed adder, which provides learners with insights into the design challenges and techniques for implementing self-timed arithmetic circuits.
Data-Flow and Handshaking Protocols: Learners will learn about data-flow control and handshaking protocols used in asynchronous circuits to ensure proper data synchronization and transfer.
Critical Path Analysis: Learners may gain knowledge of how to identify and analyze critical paths in asynchronous circuits, focusing on minimizing critical path delays to improve performance.
Power-Efficient Design Considerations: The paper may discuss power-efficient design considerations for asynchronous circuits and how Transmission Gate Logic can contribute to power savings.
Delay-Insensitive Design: Asynchronous circuits often operate in a delay-insensitive manner, meaning their performance is independent of gate delays. Learners will understand how this property is achieved and its implications for circuit behavior.
Circuit Timing and Correctness Verification: Learners will learn techniques for verifying the timing and correctness of asynchronous circuits, including methods for avoiding race conditions and hazards.
Application of Asynchronous Circuits: Learners will be exposed to potential applications of asynchronous circuits, such as in low-power and high-speed computing systems or in interfacing between clock domains with different frequencies.
Analysis of Research Papers: By studying this paper, learners will develop skills in critically analyzing research papers, understanding the proposed methodologies, and evaluating the results and conclusions presented.