In this approach of designing multiplier will affects the generation of partial products and optimize the design of multiplier operator making it in a power efficient optimized booth multiplier.
In this project, a 16 bit booth multiplier was designed. Here for the implementation of the booth multiplier Radix – 16 booth encoding was considered. And later the generated partial production summation was done sequentially of each row of generated partial product. As we all aware of the fact that multipliers play a major role in various DSP blocks in VLSI. Such multiplier need to be designed efficiently. This approach of designing multiplier will affects the generation of partial products and optimize the design of multiplier operator making it in a power efficient optimized booth multiplier. Further we can enhance the design by approximating it to analyze the efficiency of the multiplier design. The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications:
Software Requirements:
· Xilinx Vivado Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes:
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills