Design of 6T, 8T & 10T ternary SRAM cells

Project Code :TVMABE218

Objective

This project proposes the design of a ternary inverter that uses low current as input voltage is VDD/2.

Abstract

This project proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 0.45 V, current supplied by a voltage source as an input voltage VDD/2 is reduced. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins. The proposed designs are all evaluated by using the 10T & 8T SRAM cells and also proved that the 8T SRAM cell based ternary logic is evaluated better compare to the 10T SRAM cell.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tool: Tanner EDA

· Technology: 45nm.

Learning Outcomes

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes:

· Introduction to Digital Electronics

· Knowledge on MOSFET operation and Characteristics

· Basics of SRAM

· Concept of Ternary Logic

o Ternary Inverters

o Ternary SRAM

· Advantages & Applications

· Tool learning in Tanner EDA

· Transistor level design of proposed block diagram

· Analysis of circuit and simulation results

· Scope of SRAM in today’s world

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice