Design of 2-bit vedic multiplier using CNTFET.

This manuscript introduces an innovative approach to designing ternary logic gates through the utilization of carbon nanotube field-effect transistors (CNTFETs). Ternary logic offers a promising departure from conventional binary logic methodologies, presenting the potential for streamlined and energy-efficient contemporary digital designs. This potential arises from reduced circuit complexities, such as interconnections and chip area. A novel design for ternary logic gates, utilizing resistive-load CNTFETs, is proposed to realize ternary logic using CNTFETs. The paper puts forth a fresh design technique for ternary logic gates grounded in CNTFETs, contrasting it with established designs of resistive-load CNTFET logic gates.

Particularly noteworthy is the amalgamation of the suggested ternary logic gate design technique with traditional binary logic gate design methods, resulting in notable enhancements in speed and power efficiency within datapath circuits like full adders and multipliers. Rigorous simulations conducted using SPICE substantiate that the proposed ternary logic gates exhibit markedly lower power consumption and delays when compared to preceding implementations of resistive-load CNTFET gates. In practical circuit applications, employing the novel ternary gates in conjunction with binary gates culminates in a remarkable reduction of over 90% in terms of the power-delay product.