Design of 16 Bit Ladner Fischer Based Modified Carry Select Adder using D-Latch

Project Code :TVMAFE643

Objective

High-Speed Addition – Utilizing the Ladner-Fischer prefix network for fast carry propagation and a modified carry select adder (CSLA) structure to reduce delay.

Abstract

ABSTRACT: Adders are crucial components in computational systems like ALUs and DSPs, with various types including Ripple Carry Adders (RCAs), Carry Look-Ahead Adders (CLAs), and Carry Select Adders (CSLAs). Each type of adder represents a different balance of area, delay, and power consumption. The CSLA strikes a middle ground between RCA and CLA, offering a moderate trade-off between area and delay. This project, titled "Implementation of High-Speed Enhanced CSLA Based on Gated D-Latch," aims to reduce area and power usage in CSLA through a gate-level optimization. The study replaces RCAs with parallel prefix adders to increase the speed of binary addition. Prefix adders, which utilize a tree structure, are known for their faster computation compared to traditional RCAs. The proposed design is evaluated by analysing logic and routing delays, using the Ladner-Fischer Parallel Prefix Adder. This enhancement boosts the CSLA's speed while optimizing both area and power. The performance of the newly developed 32-bit CSLA architecture is compared to that of the standard CSLA. The research demonstrates how integrating prefix adders can enhance CSLA design, improving both speed and efficiency.

Keywords: Carry Select Adder, Gated D-Latch, Ladner Fischer Parallel Prefix Adder.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications:

Software Requirements:

· Tool: Xilinx Vivado

· HDL: Verilog

Learning Outcomes

Learning Outcomes:

· Understanding Approximate Computing Concepts

· Analysing the Architecture of Approximate Booth Multipliers

· Evaluating Trade-offs Between Efficiency and Error Rates

· Implementing Filtration Logic in Digital Design

· Applying Truncation Techniques for Error Management

· Recognizing the Role of Encode Selection in Multiplier Performance

· Exploring Applications of Approximate Multipliers in Real-World Scenarios

· Developing Skills in Resource Optimization for Computing Hardware

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice