Design Flow for The Implementation of Obfuscated Finite State Machines

Project Code :TVMAFE553

Objective

Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation.

Abstract

Hardware obfuscation is a useful technique for IP (intellectual property) protection. Several previous works have paid attention to the design of obfuscated FSM (finite state machine). Their common way is to insert an extra obfuscation mode to prevent the attackers from entering the normal mode. Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation. The proposed design flow includes two main steps: RTL coding (for the obfuscation mode) followed by FPGA synthesis. Experiments with a real circuit show that the FPGA implementation can work without any degradation on circuit speed.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications:

Software Requirement:

· Xilix ISE for Synthesis & Simulation purpose.

Hardware Requirements:

· One can use any FPGA to dump the code like Digilent Basys-3.

Learning Outcomes

Learning Outcomes:

One can learn the below mentioned topics from this project:

· About obfuscation.

· About State Diagram.

· About Verilog HDL (Language USED in this PROJECT).

· About Xilinx ISE(Software Used in this Project).

· About FSM’s.

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice