Design and Verification of Floating Point Multiplier for DSP Applications

This paper presents the design, functional verification, and synthesis-level evaluation of a pipelined IEEE-754 single-precision floating-point multiplier, optimized for real-time digital signal processing (DSP) applications. Unlike most existing FPGA-based floating-point multipliers, the proposed design integrates a simplified Dadda-based mantissa multiplier with a carry look-ahead adder for exponent computation, supports all four IEEE-754 rounding modes, and provides complete exception handling for overflow, underflow, invalid, and inexact results. The design consists of three pipeline stages and incorporates a dedicated rounding unit, with special emphasis on correct handling of subnormal numbers, zero, infinity, and NaN (Not a Number) cases. Functional verification is carried out using a self-checking Verilog testbench that validates the design across standard and edge-case scenarios. In addition to simulation, the RTL was synthesized and analyzed using Xilinx Vivado 2018.2 targeting the Artix-7 FPGA (Nexys A7-100T, xc7a100tcsg324-1). Timing optimization was explored by introducing a pipeline register in the multiplier stage to improve maximum frequency. The design achieves timing closure and efficient resource utilization, indicating readiness for FPGA deployment in embedded and DSP domains