Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

Also Available Domains DSP Core|Xilinx Vivado

Project Code :TVMATO733

Objective

The main aim of this paper is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras reduce computation delay and improve the performance of the RISC design.

Abstract

In this project, a Vedic mathematics based multiplier for a 16 bit is implemented which ia a part in ALU of RISC processor. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. Here the RISC V processor with very brief details are included and based on that the designing of RISC V processor is done without considering any deep architecture involved in the ROSC V processor as our main focus is to design a multiplier and MAC based on Vedic sutras and that need to be applied in processors. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and apply it for higher bits and efficient way compared to existing method such as Array multiplier. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay and saves power compared to conventional Array multiplier based processor. Hence the improvement in parameters can be analyzed. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7 Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to Arithmetic circuits
Knowledge on MAC unit
Different control units and instructions
Knowledge on RISC processor
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Related Projects

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
Testing
DSP Core
Communications
Nano Technology

Back End Domains

Cadence EDA
Transistor Logic
Core Memories
Low Power VLSI

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice