Design and Synthesis of Combinational Circuits using Reversible Decoder In Xilinx

In this project, we are implementing full adder, full subtractor, and multiplexer, binary comparator using a novel reversible decoder. Reversible logics are one of the most vital logics in present and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, digital signal processing etc., Logic synthesis for reversible logic differs considerably from standard logic synthesis. Reversible logic has been motivated by consideration of zero-energy computation thus it reduces the power utilization. These Reversible logics are used to design combinational circuits like Decoders; Multiplexers have better performance compared to the conventional systems.  In this paper the design analysis of implemented reversible multiplexer and decoder is presented. All arithmetic and logic modules are implemented in reversible multiplexer logic by which delay is reduced along with power consumption.