Design and Simulation of a Carry Save Adder (CSA) using NAND Gate in CMOS 180nm Technology
Also Available Domains Nano Technology|Transistor Logic|Low Power VLSI
Objective
The objective of this project is to design and simulate a Carry Save Adder (CSA) using NAND gates in CMOS 180nm technology for high-speed arithmetic computation. It focuses on optimizing the adder design to achieve reduced propagation delay and efficient power utilization. The CSA will be implemented using only NAND gates to demonstrate the universality and compactness of logic design. Simulation will be performed to verify functionality, timing, and power performance at the transistor level. The overall goal is to develop a fast and area-efficient adder architecture suitable for VLSI and digital signal processing applications.
Paper Publishing
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