Design and Simulation of a 16 Bit Ultra Low Power SAR ADC with Digital Calibration Using 180 nm CMOS

This paper offers a comprehensive guide to low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It delves into the operational principles, error analysis, and practical design considerations for these devices. Additionally, the paper provides an extensive review of cutting-edge low-power techniques applied to each component within the SAR ADC architecture, encompassing comparators, capacitive digital-to-analog converters (DACs), and SAR logic circuits. The primary objective of this work is to serve as a valuable resource for SAR ADC designers aiming to enhance energy efficiency in low-to-medium speed applications.

The design is implemented using 250nm CMOS process technology. Simulation and verification are performed using Tanner EDA tool. The results indicate that the proposed 16-bit SAR ADC achieves the desired resolution and meets the specified performance requirements. The ADC exhibits low power consumption, and satisfactory performance. This design can find applications in various fields requiring high-precision analog-to-digital conversion, such as medical imaging, scientific instrumentation, and communication systems.

Keywords: Analog-to-digital converter (ADC), successive approximation register (SAR), low power, energy efficiency