Design and Performance Analysis of CMOS, GDI, and PTL Logic Gates at 90nm Technology

This work investigates and compares three logic design styles — Static CMOS, Gate Diffusion Input (GDI), and Pass Transistor Logic (PTL) — for basic logic gates (e.g., AND, OR, XOR, INV) in a 90 nm CMOS technology. Using Cadence Virtuoso for schematic design and simulation, we model and simulate each logic gate under the same process parameters, running DC, transient, and AC analyses. We evaluate performance in terms of propagation delay, power consumption (static and dynamic), power-delay product (PDP), transistor count (area proxy), and output voltage swing. Our results indicate that GDI-based designs achieve significant reductions in transistor count and power, consistent with previous studies showing up to ~45 % area reduction in 90 nm GDI circuits. PTL gates offer compact designs with lower delay in some cases, but suffer from degraded voltage levels due to threshold loss. The study highlights the design-tradeoffs between robustness (CMOS), low-power/area (GDI), and speed/compactness (PTL), and discusses when each style might be preferable in nanoscale VLSI circuits.