Design and performance analysis of 4-bit ALU for Nano- Processor design for low area, Low power and minimum delay using 32nm CMOS technology

Although modern VLSI chip technologies have advanced in terms of transistor and device parameter scaling, regulating current between the source and drain terminals remains a difficult task. CMOS transistors have been integrated into VLSI chips to allow for effective control of device current. This article addresses challenges in CMOS technology, with a focus on the planned 4-bit Nano CPU employing CMOS 32nm technology and the Tanner eda tool. The proposed Nano processor begins with a 4bit ALU that incorporates all fundamental and universal gates, an efficient and high-speed adder, multiplier, and multiplexer. The major subcomponents that can be changed are the Carry Save Adder (CSA) and the multiplier. Power consumption and area reduction should be optimised.

Finally, DRC and LVS are used for verification and validation before the final chip-level circuit is developed for chip production. The ALU is developed with CMOS inverters, and the ALU schematic is simulated using a 32nm CMOS technical library and compared to CMOS technology, which is simulated using a 32nm CMOS library (without CMOS). AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder, and ANN consume 36.09nW, 64.970nW, and ANN respectively. Power consumption and area reduction should be optimised. The proposed Nano processor's second component is a 4-bit 6T SRAM, encoder and decoder, and an Artificial Neural Network (ANN). All of these subcomponents are created at the analogue transistor level (Schematic level), and the Graphic Data System (GDS-II) is generated using mask layout design.

Finally, DRC and LVS are used for verification and validation before the final chip-level circuit is developed for chip production. The ALU is developed with CMOS inverters, and the ALU schematic is simulated using a 32nm CMOS technical library and compared to CMOS technology, which is simulated using a 32nm CMOS library (without CMOS).

Keywords: —— CMOS Technology, CMOS, Gated Techniques, ANN, CSA, Nano Processors