Design and Optimization of 8 bit ALU using Reversible Logic

Conventional CMOS circuits dissipate energy through the loss of information bits. This energy dissipation, manifesting as power consumption, is a critical factor in low-power design. Modern digital circuits increasingly rely on Reversible Logic to address this issue. Reversible Logic minimizes heat dissipation, facilitates nearly energy-free computation, enables higher circuit densities, and enhances fault detection capabilities.

This paper introduces a novel design for a Reversible 8-bit Arithmetic Logic Unit (ALU), constructed by cascading 1-bit ALUs. Each 1-bit ALU comprises two primary components: the control unit and the adder unit. The Control Output Gate (COG) is utilized for the control unit, while the Haghparast and Navi Gate (HNG) is employed for the adder unit.

Compared to existing designs, the proposed ALU achieves a reduced gate count and transistor count, showcasing its efficiency. Moreover, the propagation delay of the proposed design is significantly lower. The design was simulated and verified using the Cadence 90nm technology software tool, affirming its effectiveness and practicality.

Keywords: Reversible logic, ALU (Arithmetic and Logic Unit), power dissipation, garbage output, COG gate, HNG gate