Design and Investigation of a Delay-Controlled 8-Bit ALU

The primary objective of “Design and investigation of a delay controlled ALU employing FinFET & CNTFET technologies” is to develop and evaluate a reconfigurable arithmetic logic unit (ALU) with controllable delay characteristics that achieves improved performance over conventional ALUs. This research focuses on integrating novel full-adder structures—such as Carry Output Predicted Adders (COPA) and Carry Input Selective Adders (CISA)—with FinFET and Carbon Nanotube Field Effect Transistor (CNTFET) technologies to construct a delay-controlled ALU that can perform arithmetic and logical operations with reduced power consumption and latency. Through simulation on an 18 nm process using Cadence Virtuoso, the design demonstrates significantly lower power usage and delay compared to traditional implementations, making it suitable for low-power, high-efficiency digital circuit applications.