Design and Implementation of vedic Multiplier an Improved Carry Increment Adder
Objective
In this paper, design of Vedic multiplier is presented using carry increment adder (CIA) logic for addition of partial product terms in partial product lines.
Abstract
To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. In this paper, design of Vedic multiplier is presented using carry increment adder (CIA) logic for addition of partial product terms in partial product lines. The multiplier presented in this paper were modeled using VERILOG HDL for 8-bit data. Previously in the literature, performance analysis was carried out between conventional multiplier designs. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption with conventional multipliers.
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Block Diagram
Specifications
Specifications:
Software Requirements:
· Xilinx vivado2018.3 Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to Arithmetic circuits
- Knowledge on MAC unit
- Different control units and instructions
- Knowledge on RISC processor
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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