DESIGN AND IMPLEMENTATION OF LOW POWER VCO USING PSEUDO NMOS LOGIC FOR PLL

Project Code :TVMATO1147

Objective

In this article, presenting novel design of PLL using modified VCO. Here, the VCO block is redesigned using Pseudo NMOS configuration.

Abstract

In this article, presenting novel design of PLL using modified VCO. Here, the VCO block is redesigned using Pseudo NMOS configuration. The working of Pseudo NMOS approach is discussed in further chapters. In conventional, the CSVCO is designed using CMOS Logic. Here, the PLL structure remains same. The Pseudo NMOS structure is applied to only VCO block. By modifying this structure, here simulating this modified complete PLL structure in the Cadence Virtuoso using GPDK 45nm.

Keywords: Pseudo NMOS logic, CSVCO (Current Starved Voltage Controlled Oscillator).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Tool: Cadence Virtuoso
Technology: GPDK 45nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

· Introduction to Analog & Digital Electronics

· Necessity of PLL.

· Advantages & Applications of PLL.

· Basics of VCO

o Different configurations of VCO

· Knowledge on Low pass filter

· Design of PLL in Cadence

· Analysis of simulation results & Outputs

· Scope of PLL in today’s world.

· Real time applications of PLL.

Demo Video

https://youtu.be/u1u1R03GHhQ?si=uIjJvq0CdQgTXQ7k

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice